LTC1698IGN datasheet(10/24 Pages) LINER

10 / 24 page

LTC1698

1698f

APPLICATIO S I FOR ATIO

Undervoltage Lockout

In UVLO (low VDD voltage) the drivers FG and CG are shut

off and the pins OPTODRV, VAUX, PWRGD and ICOMP are

forced low. The LTC1698 allows the bandgap and the

internal bias currents to reach their steady-state values

before releasing UVLO. Typically, this happens when VDD

reaches approximately 4.0V. Beyond this threshold, the

drivers start switching. The OPTODRV, VAUX, PWRGD and

ICOMP pins return to their normal values and the chip is

fully functional. However, if the VDD voltage is less than 7V,

the OPTODRV and VAUX current sourcing capabilities are

limited. See the OPTO driver graphs in the Typical Perfor-

mance Characteristics section.

VDD Regulator

The bias supply for the LTC1698 is generated by peak

rectifying the isolated transformer secondary winding. As

shown in Figure 2, the zener diode Z1 is connected from

base of Q5 to ground such that the emitter of Q5 is

regulated to one diode drop below the zener voltage. RZ is

selected to bring Z1 into conduction and also provide base

current to Q5. A resistor (on the order of a few hundred

ohms), in series with the base of Q5, may be required to

surpress high frequency oscillations depending on Q5’s

selection. A power MOSFET can also be used by increasing

the zener diode value to offset the drop of the gate-to-

source voltage. VDD supply current varies linearly with the

supply voltage, driver load and clock frequency. A 4.7

µF

bypass capacitor for the VDD supply is sufficient for most

applications. This capacitor must be large enough to

provide a stable DC voltage to meet the LTC1698 VDD

supply requirement. Under start-up conditions, it must be

small enough to power up instantaneously, enabling the

LTC1698 to regulate the feedback loop. Using a larger

capacitor requires evaluation of the start-up performance.

SYNC Input

Figure 3 shows the synchronous forward converter appli-

cation. The primary controller LT3781 runs at a fixed

frequency and controls MOSFETs Q1 and Q2. The second-

ary controller LTC1698 controls MOSFETs Q3 and Q4. An

inexpensive, small-size pulse transformer T2 synchro-

nizes the primary and the secondary controllers. Figure 4

shows the pulse transformer timing waveforms. When the

LT3781 synchronization output SG goes low, MOSFET

VSECONDARY

Ω

RB*

*RB IS OPTIONAL, SEE TEXT

10V

FZT690

0.47

µF

4.7

µF

1698 F02

VDD

Figure 2. VDD Regulator

••

VIN

PRIMARY

CONTROLLER

LT3781

SECONDARY

CONTROLLER

LTC1698

COUT

VOUT

FG SYNC

CSG

ISOLATION BARRIER

SECONDARY

PRIMARY

CSYNC

RSYNC

1698 F03

Figure 3. Synchronization Using Pulse Transformer

SYNC

1698 F04

Figure 4. Primary Side and Secondary Side

Synchronization Waveforms

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