V62SLASH12615-01XE-R datasheet(30/98 Pages) TI1

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CRS_DV

RXD[1:0]

RX_ER

T2.27.2

T2.27.1

T2.27.2

PMD Input Pair

T2.27.3

T2.27.5

RX_DV

T2.27.2

IDLE

(J/K)

Data

(TR)

Data

T2.27.4

DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Specifications

(1)

Per the RMII Specification, output delays assume a 25-pF load.

(2)

CRS_DV is asserted asynchronously in order to minimize latency of control signals through the why. CRS_DV may toggle

synchronously at the end of the packet to indicate CRS deassertion.

(3)

RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.

4.7.27 RMII Receive Timing

PARAMETER

DESCRIPTION

NOTES(1) (2) (3)

MIN

TYP

MAX

UNIT

T2.27.1

X1 clock period

50-MHz reference clock

T2.27.2

RXD[1:0], CRS_DV, RX_DV and

RX_ER output delay from X1 rising

T2.27.3

CRS ON delay

From JK symbol on PMD receive

pair to initial assertion of

CRS_DV

18.5

bits

T2.27.4

CRS OFF delay

From TR symbol on PMD

receive pair to initial deassertion

of CRS_DV

bits

T2.27.5

RXD[1:0] and RX_ER latency

From symbol on receive pair.

Elasticity buffer set to default

value (01).

bits

Figure 4-28. RMII Receive Timing

V62/12615-01XE-R Datasheet(PDF) 30 Page - Texas Instruments

V62/12615-01XE-R Datasheet(HTML) 30 Page - Texas Instruments

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