V62SLASH12615-01XE-R datasheet(58/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

5.6.1

In the register definitions under the ‘Default’ heading, the following definitions hold true:

•

RW = Read Write access

•

SC = Register sets on event occurrence and Self-Clears when event ends

•

RW/SC = Read Write access/Self-Clearing bit

•

RO = Read Only access

•

COR = Clear on Read

•

RO/COR = Read Only, Clear on Read

•

RO/P = Read Only, Permanently set to a default value

•

LL = Latched Low and held until read, based upon the occurrence of the corresponding event

•

LH = Latched High and held until read, based upon the occurrence of the corresponding event

5.6.1.1

Basic Mode Control Register (BMCR)

Table 5-9. Basic Mode Control Register (BMCR), Address 0x00

BIT

BIT NAME

DEFAULT

DESCRIPTION

Reset

0, RW/SC

Reset:

1 = Initiate software Reset/Reset in Process.

0 = Normal operation.

This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is re-strapped.

Loopback

0, RW

Loopback:

1 = Loopback enabled.

0 = Normal operation.

The loopback function enables MII transmit data to be routed to the MII

receive data path.

Setting this bit may cause the descrambler to lose synchronization and

produce a 500-µs dead time before any valid data will appear at the MII

receive outputs.

Speed Selection

Strap, RW

Speed Select:

When auto-negotiation is disabled writing to this bit allows the port speed

to be selected.

1 = 100 Mbps.

0 = 10 Mbps.

Auto-Negotiation Enable

Strap, RW

Auto-Negotiation Enable:

Strap controls initial value at reset.

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored

when this bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed

and duplex mode.

Power Down

0, RW

Power Down:

1 = Power down.

0 = Normal operation.

Setting this bit powers down the PHY. Only the register block is enabled

during a power down condition. This bit is OR’d with the input from the

PWR_DOWN/INT pin. When the active low PWR_DOWN/INT pin is

asserted, this bit will be set.

Isolate

0, RW

Isolate:

1 = Isolates the Port from the MII with the exception of the serial

management.

0 = Normal operation.

V62/12615-01XE-R Datasheet(PDF) 58 Page - Texas Instruments

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