V62SLASH12615-01XE-R datasheet(76/98 Pages) TI1

76 / 98 page

RJ45

RD–

RD+

TD–

TD+

RD-

RD+

TD-

TD+

1:1

0.1μF*

1:1

49.9

Ω

49.9Ω

0.1μF*

Vdd

NOTE: Center tap is pulled to V

DD.

0.1µF

All values are typical and are +/- 1%

Vdd

49.9

Ω

49.9Ω

0.1µF

Vdd

*Place capacitors close to the

transformer center taps.

Place resistors and

capacitors close to

the device.

Common mode chokes

may be required.

DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Application and Implementation

Figure 6-2. 10/100 Mbps Twisted Pair Interface

6.2.1.2

Clock IN (X1) Requirements

The DP83848-EP supports an external CMOS level oscillator source or a crystal resonator device.

Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 6-1

and Table 6-2.

Crystal

A 25-MHz, parallel, 20-pF load crystal resonator should be used if a crystal source is desired. Figure 6-4

shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the

crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of

100 mW and a maximum of 500 µW. If a crystal is specified for a lower drive level, a current limiting

resistor should be placed in series between X2 and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, CL1

and CL2 should be set at 33 pF, and R1 should be set at 0 Ω.

Specification for 25-MHz crystal are listed in Table 6-3.

V62/12615-01XE-R Datasheet(PDF) 76 Page - Texas Instruments

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