V62SLASH12615-01XE-R datasheet(36/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-T mode, link is established

as a result of input receive amplitude compliant with the TPPMD specifications which will result in internal

generation of signal detect. A 10 Mbps Link is established as a result of the reception of at least seven

consecutive normal link pulses or the reception of a valid 10BASE-T packet. This will cause the assertion

of LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as specified in the IEEE

802.3 specification.

The LED_LINK pin in Mode 1 will be OFF when no LINK is present.

The LED_LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate

activity is present on either transmit or receive activity.

The LED_SPEED pin indicates 10 or 100 Mbps data rate of the port. The standard CMOS driver goes

high when operating in 100 Mbps operation. The functionality of this LED is independent of mode

selected.

The LED_ACT/COL pin in Mode 1 indicates the presence of either transmit or receive activity. The LED

will be ON for Activity and OFF for No Activity. In Mode 2, this pin indicates the Collision status of the port.

The LED will be ON for Collision and OFF for No Collision.

The LED_ACT/COL pin in Mode 3 indicates the presence of duplex status for 10-Mbps or 100-Mbps

operation. The LED will be ON for full duplex and OFF for half duplex.

In 10 Mbps half duplex mode, the collision LED is based on the COL signal.

Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the

pin is pulled up or down.

5.3.3.1

LEDs

Since the auto-negotiation (AN) strap options share the LED output pins, the external components

required for strapping and LED usage must be considered in order to avoid contention.

Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is

dependent on the logic level sampled by the corresponding AN input upon power-up/reset. For example, if

a given AN input is resistively pulled low then the corresponding output will be configured as an active

high driver. Conversely, if a given AN input is resistively pulled high, then the corresponding output will be

configured as an active low driver.

Refer to Figure 5-1 for an example of AN connections to external components. In this example, the AN

strapping results in auto-negotiation with 10/100 half or full duplex advertised.

The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual

purpose pins.

V62/12615-01XE-R Datasheet(PDF) 36 Page - Texas Instruments