V62SLASH12615-01XE-R datasheet(68/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

Table 5-20. MII Interrupt Status and Miscellaneous Control Register (MISR), Address 0x12 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

SPD_INT_EN

0, RW

Enable Interrupt on change of speed status

DUP_INT_EN

0, RW

Enable Interrupt on change of duplex status

ANC_INT_EN

0, RW

Enable Interrupt on Auto-negotiation complete event

FHF_INT_EN

0, RW

Enable Interrupt on False Carrier Counter Register half-full event

RHF_INT_EN

0, RW

Enable Interrupt on Receive Error Counter Register half-full event

5.6.2.4

False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the “False Carriers” attribute within the MAU

managed object class of Clause 30 of the IEEE 802.3u specification.

Table 5-21. False Carrier Sense Counter Register (FCSCR), Address 0x14

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

7:0

FCSCNT[7:0]

0, RO/COR

False Carrier Event Counter:

This 8-bit counter increments on every false carrier event. This

counter sticks when it reaches its max count (FFh).

5.6.2.5

Receiver Error Counter Register (RECR)

This counter provides information required to implement the “Symbol Error During Carrier” attribute within

the PHY managed object class of Clause 30 of the IEEE 802.3u specification.

Table 5-22. Receiver Error Counter Register (RECR), Address 0x15

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:8

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

7:0

RXERCNT[7:0]

0, RO/COR

RX_ER Counter:

When a valid carrier is present and there is at least one occurrence of

an invalid data symbol, this 8-bit counter increments for each receive

error detected. This event can increment only once per valid carrier

event. If a collision is present, the attribute will not increment. The

counter sticks when it reaches its max count.

5.6.2.6

100 Mbps PCS Configuration and Status Register (PCSR)

This register contains event status and enables for the interrupt function. If an event has occurred since

the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the

set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

Table 5-23. 100 Mbps PCS Configuration and Status Register (PCSR), Address 0x16

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:13

RESERVED

<00>, RO

RESERVED: Writes ignored, Read as 0

RESERVED

RESERVED: Must be zero

RESERVED

RESERVED: Must be zero

TQ_EN

0, RW

100Mbs True Quiet Mode Enable:

1 = Transmit True Quiet Mode

0 = Normal Transmit Mode

SD FORCE PMA

0, RW

Signal Detect Force PMA:

1 = Forces Signal Detection in PMA

0 = Normal SD operation

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