FSL518APG datasheet(22/27 Pages) ONSEMI

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which decreases the pulse current that charges the

capacitor every time the FSL5x8 resumes switching

operation in burst−mode.

For more information, please refer to AN−4148.

• Maximum Duty and Reflected Output Voltage

When MOSFET in FSL5x8 is turned off, the input

voltage together with the reflected output voltage (VRO)

on primary winding of the transformer are imposed on

MOSFET.

(eq. 8)

VDRAIN

max +

2 @ Vline

max )

VRO

Vlinemax is maximum ac-input voltage in r.m.s. value.

VRO is a function of maximum duty (Dmax) and minimum

DC-link voltage.

(eq. 9)

VRO +

Dmax

1 * Dmax

@ VDC

min

The designed Dmax should not exceed FSL5x8’s

maximum duty raio specification, DMAX. It is typical to

have 70% of de-rating on VDRAINmax according to

MOSFET’s breakdown voltage. With 800 V of

breakdown voltage in FSL5x8, more room are created to

target higher Dmax.

• Transformer Design Considerations

When Dmax is assigned, turn ratio of the transformer has

been decided.

(eq. 10)

n +

VRO

VOUT ) VF

where NP and NS stands for primary and secondary

windings’ turn ratio of the transformer, VOUT stands for

output voltage, and VF stands for forward voltage of

rectifying diode connecting to the secondary winding.

Inductance (Lm) of the primary winding can be

obtained from input power (Pin) and switching frequency

(fsw), with ripple factor (KRF) left to be decided. KRF ≥ 1

results in lower inductance and discontinuous-

conduction-mode (DCM) design, which tend to have

smaller switching loss. KRF < 1 results in a continuous-

conduction-mode (CCM) design. Which tend to be able

to deliver more power with same maximum drain current.

(eq. 11)

Lm +

VDC

min

@ Dmax

Pin @ fSW @ KRF

The inductance value affects maximum drain current

(IDRAINPEAK), which should be limited by FSL5x8’s ILIM

specification with some margin. Care needs to be taken

when designing Lm and choosing part from FSL5x8

series.

(eq. 12)

IDRAIN

PEAK

VDC

min

@ Dmax

VDC

min

@ Dmax

2 @ Lm @ fSW

• Clamping Circuit for internal MOSFET

Due to parasitic or leakage inductance, it is inevitable

that voltage on DRAIN pin of MOSFET shows some

spikes during switching off. A clamping circuit is

generally implemented if the spike can be so high that

makes DRAIN voltage possibly exceeds MOSFET’s

breakdown voltage, BVDSS. The clamping circuit can be

RCD snubber or transient-voltage suppressor. In both

cases, the design target is to clamp the reflected voltage

that appears across primary winding with a clamping

voltage Vclamp.

Vclamp should be set up properly considering power

loss and BVDSS of MOSFET. Vclamp is way too high,

MOSFET is likely to get damage at maximum input

voltage. Whereas, too low one could cause power loss

increasing at the clamp circuit. Generally, value in 2~2.5

times of VRO is usually chosen. Additionally, it should

not exceed over 90% of BVDSS.

(eq. 13)

2 @ Vline

max )

Vclamp v 90% @ BVDSS

AN−4137 and AN−4140 provide detailed flyback

converter, transformer, and snubber design information.

A design tool with accompanying manual is also made for

FSL5x8 series.

Figure 46. Magnetic Component and RCD Snubber

−

VIN

−

VRO

−

VDRAIN

Llk

Figure 47. Typical Waveform of DRAIN Current

and Voltage

VIN

VRO

VDS

IDRAIN

PEAK

Vclamp

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