VS6624P0LP datasheet(31/100 Pages) STMICROELECTRONICS

Part #	VS6624P0LP

Description	1.3 Megapixel Mobile Camera Module

PDF	100 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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31 / 100 page

VS6624

Data synchronization methods

Rev 1

31/100

Figure 15. VSYNC timing example

If manual mode is selected then the line number for VSYNC rising edge and falling edge is

programmable. The rising edge of VSYNC is programmed in the bVsyncRisingLine

registers, the pixel position for VSYNC rising edge is programmed in the bVsyncRisingPixel

registers. Similarly the line count for the falling edge position is specified in the

bVsyncFallingLine registers, and the pixel count is specified in the bVsyncFallingPixel

registers.

Pixel clock (PCLK)

The PCLK signal is controlled by the

Output formatter control register. The following options

are available:

●

enable/disable

●

select polarity

●

select starting phase

●

qualify/don’t qualify embedded synchronization codes

●

enable/disable during horizontal blanking

BLANKING

V=1

V=0

V=1

V=0

vsync

ACTIVE

VIDEO

ACTIVE

VIDEO

VS6624P0LP Datasheet(PDF) 31 Page - STMicroelectronics