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ADPD4200 Datasheet(PDF) 72 Page - Analog Devices

Part # ADPD4200
Description  Multimodal Sensor Front End
PDF  93 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADPD4200 Datasheet(HTML) 72 Page - Analog Devices

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Data Sheet
ADPD4200
REGISTER DETAILS
analog.com
Rev. 0 | 72 of 93
Table 27. Interrupt Status and Control Register Details
Addr
Name
Bits
Bit Name
Description
Reset Access1
3
INT_DATA_D
Time Slot D Data Register Interrupt Status. This bit is set every time
the Time Slot D data registers are updated. Write 1 to this bit to clear
the interrupt. The interrupt is cleared automatically when the Time
Slot D data registers are read if the INT_ACLEAR_DATA_D bit is set.
0x0
R/W1C
2
INT_DATA_C
Time Slot C Data Register Interrupt Status. This bit is set every time
the Time Slot C data registers are updated. Write 1 to this bit to clear
the interrupt. The interrupt is cleared automatically when the Time
Slot C data registers are read if the INT_ACLEAR_DATA_C bit is set.
0x0
R/W1C
1
INT_DATA_B
Time Slot B Data Register Interrupt Status. This bit is set every time
the Time Slot B data registers are updated. Write 1 to this bit to clear
the interrupt. The interrupt is cleared automatically when the Time
Slot B data registers are read if the INT_ACLEAR_DATA_B bit is set.
0x0
R/W1C
0
INT_DATA_A
Time Slot A Data Register Interrupt Status. This bit is set every time
the Time Slot A data registers are updated. Write 1 to this bit to clear
the interrupt. The interrupt is cleared automatically when the Time
Slot A data registers are read if the INT_ACLEAR_DATA_A bit is set.
0x0
R/W1C
0x0002
INT_STATUS_LEV0
[15:12]
Reserved
Reserved.
0x0
R
11
INT_LEV0_L
Time Slot L Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
10
INT_LEV0_K
Time Slot K Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
9
INT_LEV0_J
Time Slot J Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
8
INT_LEV0_I
Time Slot I Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
7
INT_LEV0_H
Time Slot H Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
6
INT_LEV0_G
Time Slot G Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
5
INT_LEV0_F
Time Slot F Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
4
INT_LEV0_E
Time Slot E Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
3
INT_LEV0_D
Time Slot D Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
2
INT_LEV0_C
Time Slot C Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
1
INT_LEV0_B
Time Slot B Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
0
INT_LEV0_A
Time Slot A Level 0 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
0x0003
INT_STATUS_LEV1
[15:12]
Reserved
Reserved.
0x0
R
11
INT_LEV1_L
Time Slot L Level 1 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
10
INT_LEV1_K
Time Slot K Level 1 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
9
INT_LEV1_J
Time Slot J Level 1 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
8
INT_LEV1_I
Time Slot I Level 1 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C
7
INT_LEV1_H
Time Slot H Level 1 Interrupt Status. This bit is set during a data
register update when the configured criteria is met.
0x0
R/W1C



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