ADPD4200 datasheet(21/93 Pages) AD

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Data Sheet

ADPD4200

THEORY OF OPERATION

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TIME SLOT OPERATION

Operation of the ADPD4200 is controlled by an internal configura-

ble controller that generates all the timing needed to generate

sampling regions and sleep periods. Measurements of multiple

sensors and control of synchronous stimulus sources are handled

by multiple time slots. The device provides up to 12 time slots for

multisensor applications. The enabled time slots are repeated at

the sampling rate, which is configured by the 23-bit TIMESLOT_PE-

RIOD_x bit field in the TS_FREQ register. The sampling rate is

determined by the following formula:

Sampling Rate = Low Frequency Oscillator Frequency (Hz) ÷ TIME-

SLOT_PERIOD_x

Each time slot allows the creation of one or more LED and/or

modulation pulses, and the acquisition of the photodiode or other

sensor current based on that stimulus. The operating parameters

for each time slot are highly configurable.

Figure 20 shows the basic time slot operation sequence. Each

time slot is repeated at the sampling rate, followed by an ultra low

power sleep period. By default, subsequent time slots are initiated

immediately following the end of the previous time slot. In addition,

there is an option to add an offset to the start of the subsequent

time slots using the TIMESLOT_OFFSET_x bit field as shown in

Figure 21, which shows the TIMESLOT_ OFFSET_B bit field be-

ing used to offset the start of Time Slot B. In this case, each

time slot still operates at the sampling rate, but there is a sleep

period between Time Slot A and Time Slot B. The wake period

shown in Figure 20 and Figure 21 is used to power up and

stabilize the analog circuitry before data acquisition begins. If the

TIMESLOT_OFFSET_B bit field is set to 0, the time slot starts as

soon as the previous time slot finishes.

The time slot offset is always applied to the Time Slot A start

time. For example, TIMESLOT_OFFSET_D is an offset added to

the beginning of Time Slot A, not Time Slot C, which immediately

precedes Time Slot D.

The amount of offset applied is dependent on the low frequency

oscillator used. If using the 1 MHz low frequency oscillator,

Offset = 64 × (Number of 1 MHz Low Frequency Oscillator Cycles)

× TIMESLOT_OFFSET_x

If using the 32 kHz low frequency oscillator,

Offset = 2 × (Number of 32 kHz Low Frequency Oscillator Cycles) ×

TIMESLOT_OFFSET_x

For example, if TIMESLOT_OFFSET_C is set to 0x040 and the

1 MHz low frequency oscillator is being used, the offset from the

start of Time Slot A to the start of Time Slot C is

Offset = (64 × 1 µs × 64) = 4.096 ms

The sampling rate is controlled by the low frequency oscillator.

The low frequency oscillator is driven by one of three sources as

described in the Clocking section.

If the sampling period is set too short to allow the enabled time slots

to complete, a full cycle of enabled time slot samples is skipped,

effectively reducing the overall sample rate. For example, if the

sampling rate is set to 100 Hz (10 ms period) and the total amount

of time required to complete all enabled time slots is 11 ms, the

next cycle of time slots does not begin until t = 20 ms, effectively

reducing the sampling rate to 50 Hz.

If TIMESLOT_OFFSET_x is set too short to allow the previous time

slot to finish, the time slot occurs immediately after the previous

time slot. Time slots always occur in A through L order.

Using External Synchronization for Sampling

An external signal driven to a configured GPIOx pin can be used to

wake the device from sleep instead of the TIMESLOT_PERIOD_x

counter, which allows external control of the sample rate and time.

This mode of operation is enabled using the EXT_SYNC_EN bit

and uses the GPIOx pin selected by the EXT_SYNC_GPIO bits. If

using this feature, be sure to enable the selected GPIOx pin as an

input using the appropriate GPIO_PIN_CFGx bits.

When operating with external synchronization and set in go mode,

the device enters sleep first and waits for the next external syn-

chronization signal before waking up. This external synchronization

signal is then synchronized to the low frequency oscillator and

then starts the wake-up sequence. If an additional external synchro-

nization is provided prior to completing time slot operations, it is

ignored.

Figure 20. Basic Time Slot Operation Sequence

Figure 21. Time Slot Operation with Offset Using TIMESLOT_OFFSET_B

ADPD4200 Datasheet(PDF) 21 Page - Analog Devices

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