DSP56600FMSLASHAD datasheet(51/76 Pages) NXP

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DSP56652

External Interface Module (EIM) Timing

Preliminary

MOTOROLA

DSP56652 Technical Data Sheet

2-9

EXTERNAL INTERFACE MODULE (EIM) TIMING

The EIM provides the bus interface between the DSP56652 and external memory and

peripherals. It uses the external address bus, data bus, bus control signals, and the

chip select signals.

Table 2-10

EIM External Bus Output AC Timing Specifications1

Num

Characteristics

MCU

@16.8 MHz

Unit

Min

Max

CLK rise to address and R/W valid

CLK rise to address and R/W invalid (output hold)

CLK rise to CS asserted

CLK rise to CS deasserted (output hold)

CLK fall to OE, EB asserted (read, OEA = 0),

EB asserted (write)2

015

CLK rise to OE, EB asserted (read, OEA = 1)2

015

CLK rise to OE, EB deasserted (output hold) (read)2

015

CLK rise to EB deasserted (output hold) (write, WEN = 0)

CLK fall to EB deasserted (output hold) (write, WEN = 1)

CLK fall to OE, EB asserted (WSC = 0)2

Ñ15

CLK rise to OE, EB deasserted (output hold) (WSC = 0)2

015

Data-in valid to CLK rise (setup)

CLK rise to dataÐin invalid (hold)

CLK rise to data-out valid

CLK rise to data-out invalid (output hold)

CLK rise to data-out high impedance

CLK fall to data-out valid (WSC = 0)

CLK rise to data-out invalid (output hold) (WSC = 0)

CLK rise to data-out high impedance (WSC = 0)

Note:

The following notes apply to this table:

Input and Output timings are measured at the 50% point of the waveforms. The specifications

assume a capacitive load of 50 pF.

These timings were measured with respect to the input clock edges.

EB outputs are asserted for reads if the EBC bit in the corresponding CS control register is clear.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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