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IP101G-DS-R01 Datasheet(PDF) 58 Page - List of Unclassifed Manufacturers

Part # IP101G-DS-R01
Description  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP101G-DS-R01 Datasheet(HTML) 58 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
7.4 AC Timing
7.4.1 Reset, Pin Latched-in, Clock and Power Source
Table 14 Reset, Pin Latched-in, Clock and Power Source Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
Tclk_lead
X1 input clock valid period before reset released
10
-
-
ms
Trst
Reset period
10
-
-
ms
Tclk_MII_rdy
MII/RMII clock output ready after reset released
(Pins settings are latched into IP101G this moment.)
-
-
10
ms
Tdiff
Time difference between AVDD33 and VDDIO,
DVDD_REGIN
-
-
30
ms
Tpwr_lead
All power source ready before reset released
11
-
-
ms
Tlat_s
Latched-in pin signal setup time
10
-
-
µs
Tlat_h
Latched-in pin signal hold time
2.63
-
-
ms
Figure 18 Reset, Pin Latched-In, Clock and Power Source Timing Requirements
58/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01



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