DSP5685XUM datasheet(21/64 Pages) FREESCALE

21 / 64 page

Introduction

56858 Technical Data, Rev. 6

Freescale Semiconductor

TCK

Input

Test Clock Input (TCK)—This input pin provides a gated clock to

synchronize the test logic and to shift serial data to the JTAG/OnCE

port. The pin is connected internally to a pull-down resistor.

TDI

Input

Test Data Input (TDI)—This input pin provides a serial input data

stream to the JTAG/OnCE port. It is sampled on the rising edge of

TCK and has an on-chip pull-up resistor.

TDO

Output(Z)

Test Data Output (TDO)—This tri-statable output pin provides a serial

output data stream from the JTAG/Enhanced OnCE port. It is driven in

the Shift-IR and Shift-DR controller states, and changes on the falling

edge of TCK.

TMS

Input

Test Mode Select Input (TMS)—This input pin is used to sequence

the JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

Note:

Always tie the TMS pin to VDD through a 2.2K resistor.

TRST

Input

Test Reset (TRST)—As an input, a low signal on this pin provides a

reset signal to the JTAG TAP controller. To ensure complete hardware

reset, TRST should be asserted whenever RESET is asserted. The

only exception occurs in a debugging environment, since the

Enhanced OnCE/JTAG module is under the control of the debugger. In

this case it is not necessary to assert TRST when asserting RESET.

Outside of a debugging environment RESET should be permanently

asserted by grounding the signal, thus disabling the Enhanced

OnCE/JTAG module on the device.

Note:

For normal operation, connect TRST directly to VSS. If the design is

to be used in a debugging environment, TRST may be tied to VSS through a

1K resistor.

Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA

Signal

Name

BGA

Pin No.

LQFP

Pin No.

Type

Description

DSP5685XUM Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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