DSP5685XUM datasheet(17/64 Pages) FREESCALE

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Introduction

56858 Technical Data, Rev. 6

Freescale Semiconductor

MODE B

GPIOH1

Input

Input/Output

Mode Select (MODE B)—During the bootstrap process MODE A

selects one of the eight bootstrap modes.

Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin after

the bootstrap process has completed.

MODE C

GPIOH2

Input

Input/Output

Mode Select (MODE C)—During the bootstrap process MODE A

selects one of the eight bootstrap modes.

Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after

the bootstrap process has completed.

RESET

Input

Reset (RESET)—This input is a direct hardware reset on the

processor. When RESET is asserted low, the device is initialized and

placed in the Reset state. A Schmitt trigger input is used for noise

immunity. When the RESET pin is deasserted, the initial chip operating

mode is latched from the MODE A, MODE B, and MODE C pins.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging

environment when a hardware reset is required and it is necessary not

to reset the JTAG/Enhanced OnCE module. In this case, assert

RESET, but do not assert TRST.

RSTO

Output

Reset Output (RSTO)—This output is asserted on any reset condition

(external reset, low voltage, software, or COP).

RXD0

GPIOE0

L10

Input

Input/Output

Serial Receive Data 0 (RXD0)—This input receives byte-oriented

serial data and transfers it to the SCI 0 receive shift register.

Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

TXD0

GPIOE1

L11

Output(Z)

Input/Output

Serial Transmit Data 0 (TXD0)—This signal transmits data from the

SCI 0 transmit data register.

Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

RXD1

GPIOE2

B11

107

Input

Input/Output

Serial Receive Data 1 (RXD1)—This input receives byte-oriented

serial data and transfers it to the SCI 1 receive shift register.

Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

TXD1

GPIOE3

C10

108

Output(Z)

Input/Output

Serial Transmit Data 1 (TXD1)—This signal transmits data from the

SCI 1 transmit data register.

Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that

can individually be programmed as input or output pin.

Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA

Signal

Name

BGA

Pin No.

LQFP

Pin No.

Type

Description

DSP5685XUM Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc

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