DSP5685XUM datasheet(40/64 Pages) FREESCALE

40 / 64 page

56858 Technical Data, Rev. 6

Freescale Semiconductor

4.9 Serial Peripheral Interface (SPI) Timing

1. Parameters listed are guaranteed by design.

Figure 4-23 SPI Timing 1

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time

Master

Slave

—

4-24, 4-25,

4-26, 4-27

Enable lead time

Master

Slave

tELD

—

12.5

—

4-27

Enable lag time

Master

Slave

tELG

—

12.5

—

4-27

Clock (SCLK) high time

Master

Slave

tCH

12.5

—

4-24, 4-25,

4-26, 4-27

Clock (SCLK) low time

Master

Slave

tCL

12.5

—

4-27

Data set-up time required for inputs

Master

Slave

tDS

—

4-24, 4-25,

4-26, 4-27

Data hold time required for inputs

Master

Slave

tDH

—

4-24, 4-25,

4-26, 4-27

Access time (time to data active from high-impedance state)

Slave

515

4-27

Disable time (hold time to high-impedance state)

Slave

4-27

Data valid for outputs

Master

Slave (after enable edge)

tDV

—

4-24, 4-25,

4-26, 4-27

Data invalid

Master

Slave

tDI

—

4-24, 4-25,

4-26, 4-27

Rise time

Master

Slave

—

11.5

10.0

4-24, 4-25,

4-26, 4-27

Fall time

Master

Slave

—

9.7

9.0

4-24, 4-25,

4-26, 4-27

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