DSP5685XUM datasheet(49/64 Pages) FREESCALE

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JTAG Timing

56858 Technical Data, Rev. 6

Freescale Semiconductor

4.13 JTAG Timing

Figure 4-33 Test Clock Input Timing Diagram

Table 4-14 JTAG Timing1, 3

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation,

T = 8.33ns.

Characteristic

Symbol

Min

Max

Unit

TCK frequency of operation2

2. TCK frequency of operation must be less than 1/4 the processor rate.

3. Parameters listed are guaranteed by design.

fOP

MHz

TCK cycle time

tCY

33.3

—

TCK clock pulse width

tPW

16.6

—

TMS, TDI data setup time

tDS

3—

TMS, TDI data hold time

tDH

3—

TCK low to TDO data valid

tDV

—12

TCK low to TDO tri-state

tTS

—10

TRST assertion time

tTRST

—

DE assertion time

tDE

—

TCK

(Input)

VIL

VM = VIL + (VIH – VIL)/2

VIH

tPW

tCY

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