LAN9252SLASHML datasheet(317/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 317

LAN9252

18.6.3

RESET AND CONFIGURATION STRAP TIMING

This diagram illustrates the RST# pin timing requirements and its relation to the configuration strap pins and output

drive. Assertion of RST# is not a requirement. However, if used, it must be asserted for the minimum period specified.

The RST# pin can be asserted at any time, but must not be deasserted until tpurstd after all external power supplies have

reached operational levels. Refer to Section 6.2, "Resets," on page 38 for additional information.

Note:

The clock input must be stable prior to RST# deassertion.

Note:

Device configuration straps are latched as a result of RST# assertion. Refer to Section 6.2.1, "Chip-Level

Resets," on page 39 for details.

Note:

Configuration strap latching and output drive timings shown assume that the Power-On reset has finished

first otherwise the timings in Section 18.6.4, "Power-On and Configuration Strap Timing" apply.

FIGURE 18-4:

RST# PIN CONFIGURATION STRAP LATCHING TIMING

TABLE 18-10: RST# PIN CONFIGURATION STRAP LATCHING TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

tpurstd

External power supplies at operational level to RST# deasser-

tion

trstia

RST# input assertion time

200

s

tcss

Configuration strap pins setup to RST# deassertion

200

tcsh

Configuration strap pins hold after RST# deassertion

todad

Output drive after deassertion

tcss

RST#

Configuration

Strap Pins

trstia

tcsh

Output Drive

todad



All External

Power Supplies

tpurstd

Vopp

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