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GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

4 REGISTER MAP

In the ST72F264, some register addresses and bit locations are changed. These changes

have made it possible to use the free locations to add new features.

Note: For easy software migration, two general rules have to be followed:

s

All “reserved” byte memory areas must never be “read” or “write”.

s

All “reserved” or “unused” bits must be left unchanged when accessing the byte.

4.1 REGISTER ADDRESS

These changes are classified in three groups:

1. New features added: Interrupt Controller (ITC), Main Clock Controller (MCC), Serial Com-

munications Interface (SCI), Flash Control/Status Register (FCSR).

2. CRSR (Clock, Reset, Supply Control/Status Register) has been replaced by the SICSR

(System Integrity Control/Status Register). Two bits relative to the AVD (Auxiliary Voltage

Detector) feature have been added into the SICSR register. Bits relative to the CSS are no

longer used.

SPISR (Serial Peripheral Interface Status Register) changed to SPICSR (Serial Peripheral

Interface Control Status Register). Refer to the Section 5.3.1 for more information.

3. ADC registers changed.

Please, refer to the datasheet for the description of the new features.

Note: These register address changes can be easily performed if you group all the register

definitions in a single header file.