10/13

GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

5.3 SPI

5.3.1 Control/Status register bits

The SPISR in the ST72C254 has been replaced by the SPICSR in the ST72F264 (refer to

Figure 4.). Their differences are the following ones:

s

the SPI SS pin alternate function is controlled from the MISCR2 as previously, but these

control bits have also been duplicated into the SPICSR register.

s

the Overrun flag has been added into the ST72F264 (SPICSR register).

5.3.2 HALT mode

The ST72F264 is able to exit from HALT mode through an SPI interrupt. This is not the case

in the ST72C254. To guarantee upward compatibility, if the SPI is used in slave mode, the SPI

interrupt must be masked (via the SPE or SPIE bits) during HALT mode to avoid any un-

wanted wake-up events.

5.4 10-BIT ADC

To meet application requirements for increased resolution, the ST72F264 has a 10-bit ADC

compared to the 8-bit ADC in the ST72C254. For upward compatibility, both ADCs have iden-

tical control registers and operating modes. The 8 most significant bits of the ST72F264 data

register (ADCDRH) are used in place of the ADCDR register of the ST72C254. The 8 least

significant bits of the ST72F264 data register (ADCDRL) have been added to reach a 10-bit

conversion. If ADCDRL is read first, ADCDRH is locked until read (which means that no max-

imum time is imposed between an ADCDRL read and an ADCDRH read) and a 10-bit conver-

sion will be performed. Then, ADCDRL and ADCDRH are ensured to correspond to the same

conversion.

If ADCDRH is read first, ADCDRL is lost and an 8-bit conversion equivalent to the ST72C254

one will be performed.

5.5 MISCELLANEOUS

Many new features have been added in the ST72F264 (refer to Figure 4.):

s

MCC (Main Clock Controller)

s

ITC (Interrupt Controller)

s

FSCR register (Flash Status Control Register)

s

SCI (Serial Communication Interface) peripheral

Please, refer to the datasheet for more information concerning the operation of all these fea-

tures and peripherals.