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GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264

3.4 WATCHDOG TIMINGS

In the ST72F264, the watchdog timeout does not have an exact duration as in the ST72C254.

It may vary between the min. and max. times specified in Figure 3.. To guarantee upward

compatibility, you have to take this into account when you develop your software. The reason

for this change is that the watchdog counter has been grouped with the Active-HALT counter

and SLOW mode prescaler to enhance power consumption and EMC performance.

Figure 2. Watchdog Block Diagram

In the ST72F264 datasheet, the linear relationship between the 6-bit value to be loaded in the

Watchdog Counter (CNT) and the resulting timeout duration in milliseconds is described. This

can be used for a quick calculation without taking the timing variations into account.

If more precision is needed, use the formulae in Figure 3..

RESET

WDGA

6-BIT DOWNCOUNTER (CNT)

T6

T0

WDG PRESCALER

WATCHDOG CONTROL REGISTER (WDGCR)

DIV 4

T1

T2

T3

T4

T5

12-BIT MCC

RTC COUNTER

MSB

LSB

DIV 64

0

5

6

11

MCC/RTC

TB[1:0] bits

(MCCSR

Register)