AN2641 datasheet(6/37 Pages) STMICROELECTRONICS

6 / 37 page

Overview of the CLCD controller

AN2641

6/37

Doc ID 14027 Rev 1

Overview of the CLCD controller

Main features:

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Dual 16-deep programmable 32-bit wide FIFOs for buffering incoming display data

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Supports single and dual panel mono Super Twisted Nematic (STN) displays with 4 or

8-bit interfaces

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Supports single and dual-panel color and monochrome STN displays

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Supports Thin Film Transistor (TFT) color displays

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Resolution programmable up to 1024 x 768

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15 gray-level mono, 3375 color STN, and 32K color TFT support

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1, 2, or 4 bits-per-pixel (bpp) palettized displays for mono STN

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1, 2, 4 or 8 bpp palettized color displays for color STN and TFT

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16 bits-per-pixel (bpp) true-color non-palettized, for color STN and TFT

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24 bpp true-color non-palettized, for color TFT

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Programmable timing for different display panels

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256 entry, 16-bit palette RAM, physically arranged as a 128 x 32-bit RAM

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Frame, line and pixel clock signals

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AC bias signal for STN and data enable signal for TFT panels

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Patented gray scale algorithm

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Supports little-endian, big-endian or WinCE data formats

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LCD can support standard panel resolutions such as:

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320 x 200, 320 x 240

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640 x 200, 640 x 240, 640 x 480

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800 x 600

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1024 x 768

Types of LCD panel supported are:

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Active matrix TFT panels with up to 24-bit bus interface

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Single-panel monochrome STN panels (4-bit and 8-bit bus interface)

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Dual-panel monochrome STN panels (4-bit and 8-bit bus interface per panel)

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Single-panel color STN panels, 8-bit bus interface

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Dual-panel color STN panels, 8-bit bus interface per panel

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Compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into the

SPEAr MPU device

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