AN2641 datasheet(10/37 Pages) STMICROELECTRONICS

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CLCD panel programmable parameters

AN2641

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Doc ID 14027 Rev 1

next section. Using this technique it is possible to generate a frequency of AHB/2,

AHB/3, and AHB/4...etc. for CLCP.

●

Another choice is to use PLL2. The connection is shown in Figure 3.

–

In SPEAr600 the PLL2 output frequency can be taken directly from the clock

synthesizer.

–

In SPEAr300, an additional connection at board level is required: GPIO (1) must

be shorted to PL_CLK3.

Figure 3.

PLL2 connection for CLCD clock

2.2.1

Clock related registers

CLKSEL, bit [5] in the LCD-timing-2 register, drives CLCDCLKSEL which is the

select signal for the external LCD clock multiplexer.

Clocks per Line (CPL) field [25:16] in the LCD-Timing2 register, specifies the

number of actual CLCP clocks for each line of the LCD panel. This is the number of

PPL divided by 1 for TFT displays.

Panel Clock Divisor (PCD), bits [31:27] & [4:0] in the LCD-Timing2 register, is used

to derive the LCD panel clock frequency CLCP from the CLCDCLK frequency as

follows:

CLCP = CLCDCLK / (PCD+2)

For TFT, the PCD can be bypassed by setting the BCD bit.

Bypass pixel clock divider (BCD), bit [26] in the LCD-Timing2 register. Setting this

to 1 bypasses the PCD logic. This is mainly used for TFT displays.

Invert Output Enable (IOE) bit [14] in the LCD-Timing2 register, used to select the

active polarity of the output enable signal in TFT mode. In this mode, the CLAC pin is

RAS

ARM

Clock synthesizer

Pll1

Pll2

DDR

Control

ler

PL_CLK3

GPIO(1)

CLCD clock

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