ML2721 datasheet(21/27 Pages) MICRO-LINEAR

21 / 27 page

ML2721

January, 2000

PRELIMINARY DATASHEET

PRELIMINARY

Table 16. PLL Mode in Normal Receive Operation

Table 15. Reference Frequency Select

Table 17. PLL Charge Pump Polarity

CONTROL INTERFACES AND REGISTER DESCRIPTION (continued)

RES (Reserved) All 4 Registers

These bits are reserved. Clear these bits to 0 (zero) for

normal operation. When power is reset all of the registers’

data fields are cleared to 0 (zero).

RD0 Register #0 Only

Reference Divide Bit Zero. This bit sets the reference

division of the PLL to either 6 or 12. See Table 15.

RXCL Register #0 Only

Receive Closed Loop Bit. This bit is used in Receive mode

to put the PLL into either open loop or closed loop. See

Table 16.

TMODE Register #2 Only

This bit is used to activate the automatic filter alignment

circuitry. For normal operations this bit must be cleared to

0 (zero).

QPP Register #0 Only

This bit sets the charge pump polarity to sink or source

current. For a majority of applications this bit is cleared

(QPP = 0). For applications where an external amplifier is

in the loop filter the bit is set to 1 to change the charge

pump polarity. See Table 17.

All register values are cleared to 0 (zero). Power up is

defined as occurring when VDD

³2.0V.

The register default values are valid 1ns after power up.

ML2721 Datasheet(PDF) 21 Page - Micro Linear Corporation