LQFP176 datasheet(60/133 Pages) STMICROELECTRONICS

60 / 133 page

Electrical characteristics

SPC560B54x/6x

60/133

DocID15131 Rev 9

Note:

RAM data retention is guaranteed with VDD_LV not below 1.08 V.

Table 14. Recommended operating conditions (5.0 V)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

VSS

Digital ground on VSS_HV pins

—

VDD

(1)

Voltage on VDD_HV pins with respect to ground

(VSS)

—4.5

5.5

Voltage drop(2)

3.0

5.5

VSS_LV

(3)

Voltage on VSS_LV (low voltage digital supply)

pins with respect to ground (VSS)

—VSS  0.1 VSS + 0.1

VDD_BV

(4)

Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)

—4.5

5.5

Voltage drop(2)

3.0

5.5

Relative to VDD

3.0

VDD + 0.1

VSS_ADC

Voltage on VSS_HV_ADC0, VSS_HV_ADC1

(ADC reference) pin with respect to ground

(VSS)

—VSS  0.1 VSS + 0.1

VDD_ADC

(5)

Voltage on VDD_HV_ADC0, VDD_HV_ADC1

(ADC reference) with respect to ground (VSS)

—4.5

5.5

Voltage drop(2)

3.0

5.5

Relative to VDD VDD  0.1 VDD + 0.1

VIN

Voltage on any GPIO pin with respect to ground

(VSS)

—VSS  0.1

—

Relative to VDD

—VDD + 0.1

IINJPAD

Injected input current on any pin during

overload condition

—

55

IINJSUM

Absolute sum of all injected input currents

during overload condition

—

50

TVDD

VDD slope to ensure correct power up

(6)

—3.0(7)

250 x 103

(0.25

[V/µs])

V/s

100 nF capacitance needs to be provided between each VDD/VSS pair.

Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog

electrical characteristics will not be guaranteed to stay within the stated limits.

330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.

470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed

depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should be less

than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode.

100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.

Guaranteed by device validation.

Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).

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