LQFP176 datasheet(11/133 Pages) STMICROELECTRONICS

11 / 133 page

DocID15131 Rev 9

11/133

SPC560B54x/6x

Block diagram

132

Table 3 summarizes the functions of the blocks present on the SPC560B54/6x.

Table 3. SPC560B54/6x series block summary

Block

Function

Analog-to-digital converter

(ADC)

Converts analog voltages to digital values

Boot assist module (BAM)

A block of read-only memory containing VLE code which is executed according

to the boot mode of the device

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Clock monitor unit (CMU)

Monitors clock source (internal and external) integrity

Cross triggering unit (CTU)

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Crossbar switch (XBAR)

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus

width.

Deserial serial peripheral

interface (DSPI)

Provides a synchronous serial interface for communication with external devices

Enhanced direct memory

access (eDMA)

Performs complex data transfers with minimal intervention from a host processor

via “n” programmable channels

Enhanced modular input output

system (eMIOS)

Provides the functionality to generate or measure events

Error correction status module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset status

information on memory errors reported by error-correcting codes

Flash memory

Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area

network)

Supports the standard CAN communications protocol

Frequency-modulated phase-

locked loop (FMPLL)

Generates high-speed system clocks and supports programmable frequency

modulation

Inter-integrated circuit (I2C) bus

Two-wire bidirectional serial bus that provides a simple and efficient method of

data exchange between devices

Internal multiplexer (IMUX) SIU

subblock

Allows flexible mapping of peripheral interface on the different pins of the device

Interrupt controller (INTC)

Provides priority-based preemptive scheduling of interrupt requests

JTAG controller (JTAGC)

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINFlex controller

Manages a high number of LIN (Local Interconnect Network protocol) messages

efficiently with a minimum of CPU load

Memory protection unit (MPU)

Provides hardware access control for all memory references generated in a

device

LQFP176 Datasheet(PDF) 11 Page - STMicroelectronics

LQFP176 Datasheet(HTML) 11 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL