SC14CVMDECT datasheet(33/57 Pages) DIALOG

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Datasheet

Revision 3.0

28-Jul-2015

CFR0011-120-00-FM Rev 5

33 of 57

SC14CVMDECT SF

Cordless Voice Module

FINAL

Note 13: Push/pull or open drain function is controlled from the sub-block’s DSP_PCM_CTRL_REG, resp. ACCESSx_CTRL_REG.

Note 14: To enable outputs, the corresponding P2_DIR_REG[y] bit(s) do not have to be controlled, this is done by the sub block.

11-10

R/W

P2_5_MODE

00 = P2_OUT_DATA_REG[5] on P2[5]

01 = PCM_FSC on P2[5]

10 = SF on P2[5]

11 = Reserved

9-8

R/W

P2_4_MODE

00 = P2_OUT_DATA_REG[4] on P2[4]

01 = PCM_DO on P2[4] (Note 13)

10 = SCL1 on P2[4] (Note 14)

11 = DP3 on P2[4]

7-6

R/W

P2_3_MODE

00 = P2_OUT_DATA_REG[3] on P2[3]

01 = PCM_DI input on P2[3]

10 = SDA1 on P2[3] (Note 14)

11 = DP2 on P2[3]

5-4

R/W

P2_2_MODE

00 = P2_OUT_DATA_REG[2] on P2[2].

01 = PCM_CLK on P2[2]

10 = CLK100 on P2[2]

11 = Reserved

3-2

R/W

P2_1_MODE

00 = P2_OUT_DATA_REG[1] on P2[1]

01 = ECZ2 (from DSP) on P2[1]

10 = Timer 0 PWM1 on P2[1]

11 = LED4 mode on P2[1]. PAD_CTRL_REG[P21_OD] must kept

‘1’ if LED is connected to VBAT. Set PAD_CTRL_REG

[LED4_PWM] = 1 for PWM on LED4 current source.

1-0

R/W

P2_0_MODE

00 = P2_OUT_DATA_REG[0] on P2[0]

01 = ECZ1 (from DSP) on P2[0]

10 = Timer0 PWM0 on P2[0]

11 = LED3 mode on P2[0]. PAD_CTRL_REG[P20_OD] must kept

‘1’ if LED is connected to VBAT. Set PAD_CTRL_REG

[LED3_PWM] =1 for PWM on LED4 current source.

NOTE: This register is not reset with a SW reset

Table 15: P3_MODE_REG (0xFF4868)

Bit

Mode

Symbol

Description

Reset

15-14

R/W

P3_7_MODE

00 = P3_OUT_DATA_REG[7] on P3[7]

01 = Analog mode RINGp on P3[7] (Note 15)

1x = Reserved

13-12

R/W

P3_6_MODE

00 = P3_OUT_DATA_REG[6] on P3[6]

01 = Analog mode RINGn on P3[6] (Note 15)

1x = Reserved

11-10

R/W

P3_5_MODE

00 = P3_OUT_DATA_REG[5] on P3[5]

01= Analog mode RINGING/RINGout on P3[5] (Note 15)

1x = Reserved

9-8

R/W

P3_4_MODE

00 = P3_OUT_DATA_REG[4] on P3[4].

01 = Analog mode PARAdet on P3[4]

1x = Reserved

7-6

R/W

P3_3_MODE

00 = P3_OUT_DATA_REG[2] on P3[3]

ADC0 input disabled, input up to VDD+0.3 V

01 = Analog ADC0 mode, input up to 1.98 V!!

1x = Reserved

5-4

R/W

P3_2_MODE

00 = P3_OUT_DATA_REG[2] on P3[2]

01 = Analog mode CIDINp on P3[2]

1x = Reserved

Table 14: P2_MODE_REG (0xFF4858)

BIT

MODE

SYMBOL

DESCRIPTION

RESET

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