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LAN9252/ML Datasheet(PDF) 270 Page - Microchip Technology |
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LAN9252/ML Datasheet(HTML) 270 Page - Microchip Technology |
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270 / 329 page  LAN9252 DS00001909A-page 270 2015 Microchip Technology Inc. 12.14.59.5 FMMUx Physical Start Address Register Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.59.6 FMMUx Physical Start Bit Register 12.14.59.7 FMMUx Type Register Offset: FMMUx Base Address +8h-9h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Physical Start Address (Mapped to logical start address) R/W RO 0000h Offset: FMMUx Base Address +Ah Size: 8 bits Bits Description ECAT Type PDI Type Default 7:3 RESERVED Write as 0. RO RO 00000b 2:0 Physical Start Bit Physical starting bit as target of logical start bit mapping (bits are counted from least significant bit (0) to most significant bit (7)). R/W RO 000b Offset: FMMUx Base Address +Bh Size: 8 bits Bits Description ECAT Type PDI Type Default 7:2 RESERVED Write as 0. RO RO 000000b 1 Write Access Mapping 0: Ignore mapping for write accesses 1: Use mapping for write accesses R/W RO 0b 0 Read Access Mapping 0: Ignore mapping for read accesses 1: Use mapping for read accesses R/W RO 0b |
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