HDMP-1012 datasheet(37/42 Pages) HP

37 / 42 page

609

the flag input to signify the two

frames. The setup and hold times

are referenced to 1/2 frame

period of D0-D19, or 90 deg,

from the edges of STRBIN. The

multiplexer delay, tmux, should be

considered for timing margins.

The STRBOUT is derived from the

internal sampling clock, and thus

has a frequency double that of

STRBIN. The falling edge of

STRBOUT appears after the rising

and falling edges of STRBIN after

a delay of Tstrb. Other interlacing

techniques can also be achieved

with edge-triggered latches for

improved timing margins.

In the Rx side, the frame D0-D19

are demultiplexed back to the

original C0-C19, and C20-C39

frames with the use of external

edge-triggered flip-flops. The

toggle clock of the flip-flops,

RCLK, is derived by the state of

the FLAG bit. RCLK toggle with

the rising edge of STRBOUT with

a delay of tda. The two frames

appear with the rising and falling

edges of RCLK with a delay of tdb.

All of the synchronous outputs

and state machine outputs appear

after the falling edge of STRBOUT

with delays of td1 and td2

respectively.

The lower frame of C0-C19 can

be delayed further with additional

latches so that both C0-C19 and

C20-C39 frames are synchronous.

Supply Bypassing and

Integrator Capacitor

Figure 20 shows the location of

the PLL integrator capacitors,

power supply capacitors and

required grounding for the Tx and

Rx chips.

Integrating Capacitor

The integrating capacitors (C2)

are required by both the Tx and

Rx to function properly. These

caps are used by the PLL for

frequency and phase lock and

directly set the stability and

lockup times. The designed value

of C2 is 0.1

µF, with a tolerance

± 10%. The internal charging

currents are scaled with the DIV0

and DIV1 settings such that the

same capacitor value works with

all four frequency bands. Larger

values of C2 improve jitter

performance, but extend the

lockup times.

Power Supply Bypassing and

Grounding

The G-LINK chip set has been

tested to work well with a single

Figure 19. Transmitter and Receiver Data Interface and Timing for Double Frame Mode (MDFSEL=0).

CONFIGURATIONS

CAV*, DAV*

PLL

C00 - C19

STRBOUT

STRBIN

CONFIGURATIONS

CAV*, DAV*, FF

LINKRDY,

ERROR

C00 - C19

STRBOUT

STAT0

STAT1

tstrb

CAV*, DAV*

STRBOUT

STRBIN

FLAG

CAV*, DAV*

FF, LINKRDY

ERROR

D00 - D19

STRBOUT

td1

ts = SETUP TIME

th = HOLD TIME

tstrb = STRBIN TO STRBOUT DELAY

tmux = 2:1 MULTIPLEXER DELAY

td1 = STRBOUT TO SYNCHRONOUS OUTPUTS DELAY

td2 = STRBOUT TO STATE MACHINE OUTPUTS DELAY

tda = STRBOUT TO RCLK DELAY

tdb = RCLK TO C00-C39 OUTPUT DELAY

2:1

MUX

D00 - D19

C20 - C39

D00 - D19

FLAG

1/2 FRAME

PERIOD

1/2 FRAME

PERIOD

D00 - D19

C00 - C19

C20 - C39

C00 - C19

C20 - C39

tmux

td2

STAT0

STAT1

FLAG

RCLK

C00 - C19

C20 - C39

C00 - C19

C20 - C39

tda

tdb

RCLK

HDMP-1012 Datasheet(PDF) 37 Page - Agilent(Hewlett-Packard)

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