HDMP-1012 datasheet(15/42 Pages) HP

15 / 42 page

587

Tx I/O Definition

Name

Type

Signal

CAP0A

Loop Filter Capacitor: CAP0A should be shorted to CAP0B. CAP1A

CAP0B

should be shorted to CAP1B. A loop filter capacitor of 0.1

µF must be

CAP1A

connected across the CAP0 and CAP1 inputs to increase the loop time

CAP1B

constant.

CAV*

I-ECL

Control Word Available Input: This active-low input tells the chip

that the user is requesting a control word be transmitted. This pin

should only be asserted after the user has determined the RFD line is

active for a given frame cycle. When this pin is asserted, the

information on the Data inputs is sent as a control frame. If CAV and

DAV are asserted simultaneously, CAV takes precedence.

I-ECL

Data Inputs: 20 Bit data is encoded and transmitted when M20SEL

is active; otherwise the 16 least significant bits are encoded and

transmitted. The encoded bits are transmitted LSB first. (e.g.: D0 is

sent first, through to either D15 or D19, followed by the 4 coding bits

C0-C3.)

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

DAV*

I-ECL

Data Available Input: This active-low input tells the chip that the

user has valid data to be transmitted. This pin should be asserted only

after the user has determined that the RFD line is active for a given

frame cycle. When this pin is asserted, the information on the Data

and Flag inputs is encoded and sent as a Data frame.

DIV0

I-ECL

VCO Divider Select: These two pins program the VCO divider chain

DIV1

to operate at full speed, half speed, quarter speed or one-eighth speed.

DOUT

O-BLL

Normal Serial Data Output: Output used when LOOPEN is not

DOUT*

active. This output is a special buffer line logic driver, which is a 50

Ω

back-terminated ECL compatible output.

ECLGND

ECL Ground: Normally 0 volts. This ground is used for the ECL pad

drivers. For best performance, coupling of the noisy ECLGND to the

clean GND and HGND grounds be minimized.

I-ECL

Enable Data: This signal comes from the Rx chip state machine and

is used to control the RFD output of the Tx chip. The state machine

only allows data to be enabled when both sides of the link have

established stable lock.

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