HDMP-1012 datasheet(41/42 Pages) HP

41 / 42 page

613

Likewise, the Vtt plane must also

be bypassed equally well.

In the positive 5 V supply

configuration, the logic outputs

are in the PECL (positive ECL)

states. Commercial translation

chips are available which will

translate PECL between TTL and

CMOS.

Mode Options

The GLlink has several option

pins which set the modes of

operation. Common to both the

Tx and the Rx are M20SEL, DIV0,

and DIV1, FLAGSEL, and

LOOPEN. Local to the Tx are

MDFSEL, EHCLKSEL, and

HCLKON. While local to the Rx

are EQEN and TCLKSEL. These

pins are all I-ECL, and can be set

as described below.

M20SEL = 0/1 sets the width of

the frame to 16/20 bits.

DIV1 / DIV0 = set the frequency

bands of operation. Refer to the

Setting the Operating Data Rate

Range

section for frequency band

selection. It is recommended that

applications near the ends of the

bands have jumpers for DIV0 and

DIV1 inputs, so that the board

can accommodate possible lot-to-

lot band variations over the life of

the board design.

FLAGSEL = 0/1 selects either the

flag bit is reserved for error

detection by the link, or as an

extra bit available for the user.

Figure 23: Methods of Interfacing O-BLL and I-H50.

OBLL

150

Ω

IH50

Ω

150

Ω

ZO = 50 Ω

OBLL

150

Ω

IH50

150

Ω

ZO = 50 Ω

A) SINGLE-ENDED DRIVE O-BLL TO I-H50 INTERFACE

B) DIFFERENTIAL DRIVE O-BLL TO I-H50

OBLL

150

Ω

ECL

Ω

150

Ω

ZO = 50 Ω

VTT (-2 V)

130

Ω

OBLL

150

Ω

ECL

150

Ω

ZO = 50 Ω

Ω

-1.3 V

C) DIFFERENTIAL DRIVE O-BLL TO ECL

D) SINGLE-ENDED DRIVE O-BLL TO ECL

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