WM8750L datasheet(13/56 Pages) WOLFSON

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WM8750L

PP Rev 1.77 May 2003

Test Conditions

DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

ADCLRC/DACLRC propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

DACDAT setup time to BCLK rising edge

DST

DACDAT hold time from BCLK rising edge

DHT

AUDIO INTERFACE TIMING – SLAVE MODE

BCLK

DACLRC/

ADCLRC

BCH

BCL

BCY

DACDAT

ADCDAT

LRSU

LRH

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

ADCLRC/DACLRC set-up time to BCLK rising edge

tLRSU

ADCLRC/DACLRC hold time from BCLK rising edge

tLRH

DACDAT hold time from BCLK rising edge

ADCDAT propagation delay from BCLK falling edge

tDD

Note:

BCLK period should always be greater than or equal to MCLK period.

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