LIS2HH12 datasheet(21/47 Pages) STMICROELECTRONICS

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LIS2HH12

Digital main blocks

A watermark interrupt CTRL3 (22h) (INT1_FTH), CTRL6 (25h)(INT2_FTH) can be enabled

in order to read data from the FIFO and leave free memory slots for incoming data. Setting

the FIFO_CTRL (2Eh) (FTH [4:0]) to value N, the number of X, Y and Z data samples that

should be read at the rise of the watermark interrupt, in order to read the entire FIFO

content, is N + 1.

5.3.4

Stream-to-FIFO mode

In Stream-to-FIFO mode (FIFO_CTRL (2Eh)(FMODE2:0) = 011), FIFO behavior changes

according to the IG_SRC1 (31h) (IA) bit. When the IG_SRC1 (31h) (IA) bit is equal to '1'

FIFO operates in FIFO mode, when the IG_SRC1 (31h) (IA) bit is equal to '0', FIFO

operates in Stream mode.

Interrupt generator 1 should be set to the desired configuration using IG_CFG1 (30h),

IG_THS_X1 (32h), IG_THS_Y1 (33h), IG_THS_Z1 (34h).

The CTRL7 (26h) (LIR1) bit should be set to '1' in order to have latched interrupt.

5.3.5

Bypass-to-Stream mode

In Bypass-to-Stream mode (FIFO_CTRL (2Eh) (FMODE [2:0]) = '100'), X, Y and Z

measurement storage inside FIFO operates in Stream mode when IG_SRC1 (31h) (IA) is

equal to '1', otherwise FIFO content is reset (Bypass mode).

Interrupt generator 1 should be set to the desired configuration using IG_CFG1 (30h),

IG_THS_X1 (32h), IG_THS_Y1 (33h), IG_THS_Z1 (34h).

The CTRL7 (26h) (LIR1) bit should be set to '1' in order to have latched interrupt.

5.3.6

Bypass-to-FIFO mode

In Bypass-to-FIFO mode (FIFO_CTRL (2Eh) (FMODE [2:0]) = '111', FIFO behavior changes

according to the IG_SRC1 (31h) (IA) bit. When the IG_SRC1 (31h)(IA) bit is equal to '1',

FIFO operates in FIFO mode, when the IG_SRC1 (31h) (IA) bit is equal to '0', FIFO

operates in Bypass mode (FIFO content reset). If a latched interrupt is generated, FIFO

starts collecting data until the first data in the FIFO buffer is overwritten. Interrupt generator

1 should be set to the desired configuration using IG_CFG1 (30h), IG_THS_X1 (32h),

IG_THS_Y1 (33h), IG_THS_Z1 (34h).

The CTRL7 (26h) (LIR1) bit should be set to '1' in order to have latched interrupt.

5.3.7

Retrieving data from FIFO

FIFO data is read through the OUT_X_L (28h) - OUT_X_H (29h), OUT_Y_L (2Ah) -

OUT_Y_H (2Bh), OUT_Z_L (2Ch) - OUT_Z_H (2Dh) registers. A read operation by means

of serial interface of OUT_X, OUT_Y or OUT_Z output registers provides the data stored

into the FIFO. Each time data is read from the FIFO, the oldest X, Y and Z data are placed

into the OUT_X, OUT_Y and OUT_Z registers and both single read and read_burst

operations can be used.

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