LQFP176 datasheet(106/133 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC560B54x/6x

106/133

DocID15131 Rev 9

IINJ

SR — Input current Injection

Current

injection on

one ADC_1

input,

different

from the

converted

one

VDD = 3.3 V ±

10%

–5

—

VDD = 5.0 V ±

10%

–5

—

| INLP |

CC T

Absolute integral nonlinearity

– Precise channels

No overload

—

LSB

| INLX |

CC T

Absolute integral nonlinearity

– Extended channels

No overload

—

1.5

LSB

| DNL |

CC T

Absolute differential

nonlinearity

No overload

—

0.5

LSB

| EO |

CC T Absolute offset error

—

LSB

| EG |

CC T Absolute gain error

—

LSB

TUEP(7)

P Total unadjusted error for

precise channels, input only

pins

Without current injection

–6

—

LSB

With current injection

–8

—

TUEX(7)

T Total unadjusted error for

extended channel

Without current injection

–10

—

LSB

With current injection

–12

—

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified

Analog and digital VSS must be common (to be tied together externally).

VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0xFFF.

During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of

the sampling time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the

sampling clock tADC1_S depend on programming.

This parameter does not include the sampling time tADC1_S, but only the time for determining the digital result and the time

to load the result’s register with the conversion result.

Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal

divider by 2.

Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

Table 46. ADC_1 conversion characteristics (12-bit ADC_1) (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

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