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LQFP176 Datasheet(PDF) 110 Page - STMicroelectronics

Part # LQFP176
Description  Variable length encoding
PDF  133 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LQFP176 Datasheet(HTML) 110 Page - STMicroelectronics

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9tSUI
SR
D Data setup time for inputs
Master mode
43
—
—
145
—
—
ns
Slave mode
5
—
—
5
—
—
10
tHI
SR
D Data hold time for inputs
Master mode
0
—
—
0
—
—
ns
Slave mode
2(6)
——
2(6)
——
11
tSUO
(7)
CC
D Data valid after SCK edge
Master mode
—
—
32
—
—
50
ns
Slave mode
—
—
52
—
—
160
12
tHO
(7)
CC
D Data hold time for outputs
Master mode
0
—
—
0
—
—
ns
Slave mode
8
—
—
13
—
—
1.
Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.
2.
Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is
asserted. DSPI2 has only SLOW SCK available.
3.
Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before
SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4.
The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS
and internal SCK must be higher than
t
CSC to ensure positive tCSCext.
5.
The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and
internal SCK must be higher than
t
ASC to ensure positive tASCext.
6.
This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
7.
SCK and SOUT are configured as MEDIUM pad.
Table 48. DSPI characteristics(1) (continued)
No.
Symbol
C
Parameter
DSPI0/DSPI1/DSPI3/DSPI5
DSPI2/DSPI4
Unit
Min
Typ
Max
Min
Typ
Max



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