CS5397 datasheet(17/40 Pages) CIRRUS

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CS5396 CS5397

DS229PP2

and SDATA2. In Master Mode, LRCK is an output

whose frequency is equal to Fs. In Slave Mode,

LRCK is an input whose frequency must be equal

to Fs and synchronous to MCLKA/D.

Master Mode- Control Port Mode

In Master mode, SCLK and LRCK are outputs

which are internally derived from the master clock.

In the 64

× Oversampling Mode, internal dividers

will divide MCLKA/D by 4 to generate a SCLK

which is 64

× Fs and by 256 to generate a LRCK

which is equal to Fs. In the 128

× Oversampling

Mode, internal dividers will divide MCLKA/D by

4 to generate a SCLK which is 128

× Fs and by 512

to generate a LRCK which is equal to Fs. The

CS5396/97 is placed in the Master mode via the

control register.

Slave Mode - Control Port Mode

LRCK and SCLK become inputs in SLAVE mode.

LRCK must be externally derived from MCLKA/D

and be equal to Fs. It is recommended that SCLK

be equal to 64

× in the 64× Oversampling Mode and

equal to 128

× in the 128× Oversampling Mode.

Other frequencies are possible but may degrade

system performance due to interference effects.

The CS5396/97 is placed in the Slave mode via the

control register.

Synchronization of Multiple Devices -

Control Port Mode

In systems where multiple ADCs are required, care

must be taken to achieve simultaneous sampling.

The FSTART bit in register 1 controls the synchro-

nization of the internal clocks and sampling pro-

cess between the analog modulator and the digital

filter. Multiple ADCs can be synchronized if the

FSTART command is initiated on the same edge of

MCLK. This can be accomplished by re-timing the

CCLK clock with the falling edge of MCLK. This

is a relatively simple matter if the ADCs have the

same address. However, if the system requires the

devices to have individual addresses, synchroniza-

tion can be accomplished by;

1) Disable the address enable bit (ADDREN) in

2) Issue a system broadcast FSTART command

synchronized with CCLK.

3) Reset the ADDREN bit.

Power-up and Calibration - Control Port

Mode

The delta-sigma modulators settle in a matter of

microseconds after the analog section is powered,

either through the application of power or by exit-

ing the power-down mode. However, the voltage

reference will take a much longer time to reach a fi-

nal value due to the presence of external capaci-

tance on the VREF pin. A time delay of

approximately 10ms/

µF is required after applying

power to the device or after exiting a power down

state.

A calibration of the tri-level delta-sigma modulator

should always be initiated following power-up and

after allowing sufficient time for the voltage on the

external VREF capacitor to settle. This is required

to minimize noise and distortion. It is also advised

that the CS5396/97 be calibrated after the device

has reached thermal equilibrium to maximize per-

formance. A calibration sequence requires the fol-

lowing commands;

1) set the FSTART bit

2) set the GND CAL bit

3) set the CAL bit

4) Wait a minimum of 2050 LRCK periods in the

128x mode or 4100 LRCK periods in the 64x

mode.

5) Remove GND CAL

High Pass Filter -Control Port Mode

The CS5396/97 includes a high pass filter after the

decimator to remove the DC offsets introduced by

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