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LQFP64 Datasheet(PDF) 61 Page - STMicroelectronics |
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LQFP64 Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 116 page  DocID14619 Rev 13 61/116 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions 115 Figure 9. Voltage regulator capacitance connection The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 3.13: Recommended operating conditions). The internal voltage regulator requires a controlled slew rate of both VDD_HV and VDD_BV as described in Figure 10. DEVICE VSS_LV VDD_BV VDD_LV VSS_LV VDD_LV VDD_HV VSS_LV VDD_LV CREG2 (LV_COR/LV_CFLA) CREG3 CDEC2 DEVICE VDD_BV I VDD_LVn VREF VDD_HV Voltage Regulator VSS_HV VSS_LVn (supply/IO decoupling) (LV_COR/LV_PLL) |
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