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LQFP64 Datasheet(PDF) 87 Page - STMicroelectronics |
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LQFP64 Datasheet(HTML) 87 Page - STMicroelectronics |
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87 / 116 page ![]() DocID14619 Rev 13 87/116 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions 115 3.27 On-chip peripherals 3.27.1 Current consumption IINJ S R — Input current Injection Current injection on one ADC input, different from the converted one VDD = 3.3 V ± 10% 5— 5 mA VDD = 5.0 V ± 10% 5— 5 | INL | C C T Absolute value for integral non-linearity No overload — 0.5 1.5 LSB | DNL | C C T Absolute differential non-linearity No overload — 0.5 1.0 LSB | EO | C C T Absolute offset error — — 0.5 — LSB | EG | C C T Absolute gain error — — 0.6 — LSB TUEp C C P Total unadjusted error(7) for precise channels, input only pins Without current injection 20.6 2 LSB T With current injection 33 TUEx C C T Total unadjusted error(7) for extended channel Without current injection 31 3 LSB T With current injection 44 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. 2. Analog and digital VSS must be common (to be tied together externally). 3. VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. 4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. 5. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts. After the end of the sampling time ts, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock ts depend on programming. 6. This parameter does not include the sampling time ts, but only the time for determining the digital result and the time to load the result’s register with the conversion result. 7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. Table 45. ADC conversion characteristics (continued) Symbol C Parameter Conditions(1) Value Uni t Min Typ Max |
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