LQFP64 datasheet(64/116 Pages) STMICROELECTRONICS

64 / 116 page

Package pinouts and signal descriptions

SPC560B40x/50x, SPC560C40x/50x

64/116

DocID14619 Rev 13

The



VDD(STDBY)| and dVDD(STDBY)/dt system requirement can be used to define the

component used for the VDD supply generation. The following two examples describe how

to calculate capacitance size:

Example 1 No regulator (worst case)

The



VDD(STDBY)| parameter can be seen as the VDD voltage drop through the ESR

resistance of the regulator stability capacitor when the IDD_BV current required to load

VDD_LV domain during the standby exit. It is thus possible to define the maximum equivalent

resistance ESRSTDBY(MAX) of the total capacitance on the VDD supply:

ESRSTDBY(MAX) = VDD(STDBY)|/IDD_BV = (30 mV)/(300 mA) = 0.1

(d)

The dVDD(STDBY)/dt parameter can be seen as the VDD voltage drop at the capacitance

pin (excluding ESR drop) while providing the IDD_BV supply required to load VDD_LV domain

during the standby exit. It is thus possible to define the minimum equivalent capacitance

CSTDBY(MIN) of the total capacitance on the VDD supply:

CSTDBY(MIN) = IDD_BV/dVDD(STDBY)/dt = (300 mA)/(15 mV/µs) = 20µF

This configuration is a worst case, with the assumption no regulator is available.

Example 2 Simplified regulator

The regulator should be able to provide significant amount of the current during the standby

exit process. For example, in case of an ideal voltage regulator providing 200 mA current, it

is possible to recalculate the equivalent ESRSTDBY(MAX) and CSTDBY(MIN) as follows:

IULPREG

SR —

Ultra low power regulator current

provided to VDD_LV domain

——

—

IULPREGINT

CC D

Ultra low power regulator module

current consumption

IULPREG = 5 mA;

TA = 55 °C

——

100

µA

IULPREG = 0 mA;

TA = 55 °C

—

2—

IDD_BV

CC D

In-rush average current on

VDD_BV during power-up

(5)

——

—

300

(6)

VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical

value is in the range of 470 nF.

This value is acceptable to guarantee operation from 4.5 V to 5.5 V

External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in

operating range.

In-rush average current is seen only for short time (maximum 20 µs) during power-up and on standby exit. It is dependant

on the sum of the CREGn capacitances.

The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized

accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.

Table 26. Voltage regulator electrical characteristics (continued)

Symbol

Parameter

Conditions(1)

Value

Unit

Min

Typ

Max

Based on typical time for standby exit sequence of 20 µs, ESR(MIN) can actually be considered at ~50 kHz.

LQFP64 Datasheet(PDF) 64 Page - STMicroelectronics

LQFP64 Datasheet(HTML) 64 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL