LQFP64 datasheet(14/116 Pages) STMICROELECTRONICS

14 / 116 page

Block diagram

SPC560B40x/50x, SPC560C40x/50x

14/116

DocID14619 Rev 13

Memory protection unit (MPU)

Provides hardware access control for all memory references generated in a

device

Nexus development interface

(NDI)

Provides real-time development support capabilities in compliance with the

IEEE-ISTO 5001-2003 standard

Periodic interrupt timer (PIT)

Produces periodic interrupts and triggers

Real-time counter (RTC)

A free running counter used for time keeping applications, the RTC can be

configured to generate an interrupt at a predefined interval independent of the

mode of operation (run mode or low-power mode)

System integration unit (SIU)

Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System status configuration

module (SSCM)

Provides system configuration and status data (such as memory size and

status, device mode and security status), device identification data, debug

status port enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR (Automotive

Open System Architecture) and operating system tasks

Software watchdog timer (SWT)

Provides protection from runaway code

Wakeup unit (WKPU)

The wakeup unit supports up to 18 external sources that can generate interrupts

or wakeup events, of which 1 can cause non-maskable interrupt requests or

wakeup events.

Crossbar (XBAR) switch

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus

width.

Table 3. SPC560B40x/50x and SPC560C40x/50x series block summary (continued)

Block

Function

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