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LQFP64 Datasheet(PDF) 51 Page - STMicroelectronics |
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LQFP64 Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 116 page  DocID14619 Rev 13 51/116 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions 115 3.15.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 22. Table 23 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. ttr CC D Output transition time output pin(2) MEDIUM configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 —— 10 ns TCL = 50 pF — — 20 D CL = 100 pF —— 40 DCL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 —— 12 TCL = 50 pF — — 25 D CL = 100 pF —— 40 ttr CC D Output transition time output pin(2) FAST configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 —— 4 ns CL = 50 pF — — 6 CL = 100 pF —— 12 CL = 25 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 —— 4 CL = 50 pF — — 7 CL = 100 pF —— 12 1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified 2. CL includes device and package capacitances (CPKG < 5 pF). Table 21. Output pin transition times (continued) Symbol C Parameter Conditions(1) Value Unit Min Typ Max Table 22. I/O supply segment Package Supply segment 12 345 6 LBGA208(1) Equivalent to LQFP144 segment pad distribution MCKO MDOn/MSEO LQFP144 pin20–pin49 pin51–pin99 pin100–pin122 pin 123–pin19 — — LQFP100 pin16–pin35 pin37–pin69 pin70–pin83 pin 84–pin15 — — LQFP64(2) pin8–pin26 pin28–pin55 pin56–pin7 — — — 1. LBGA208 available only as development package for Nexus2+ 2. All LQFP64 information is indicative and must be confirmed during silicon validation. |
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