LQFP64 datasheet(65/116 Pages) STMICROELECTRONICS

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DocID14619 Rev 13

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SPC560B40x/50x, SPC560C40x/50x

Package pinouts and signal descriptions

115

ESRSTDBY(MAX) = VDD(STDBY)|/(IDD_BV  200 mA) = (30 mV)/(100 mA) = 0.3 

CSTDBY(MIN) = (IDD_BV  200 mA)/dVDD(STDBY)/dt = (300 mA 

200 mA)/(15 mV/µs) = 6.7 µF

In case optimization is required, CSTDBY(MIN) and ESRSTDBY(MAX) should be calculated

based on the regulator characteristics as well as the board VDD plane characteristics.

3.17.2

Low voltage detector electrical characteristics

The device implements a Power-on Reset (POR) module to ensure correct power-up

initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV

voltage while device is supplied:



POR monitors VDD during the power-up phase to ensure device is maintained in a safe

reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR

in device reference manual)



LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer

to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device

reference manual)



LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to

RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference

manual)



LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status

(RGM_DES) Register flag F_LVD12_PD1 in device reference manual



LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status

(RGM_DES) Register flag F_LVD12_PD0 in device reference manual)

Note:

When enabled, power domain No. 2 is monitored through LVDLVBKP.

Figure 12. Low voltage detector vs reset

Note:

Figure 12: Low voltage detector vs reset does not apply to LVDHV5 low voltage detector

because LVDHV5 is automatically disabled during reset and it must be enabled by software

again. Once the device is forced to reset by LVDHV5, the LVDHV5 is disabled and reset is

VDD

VLVDHVxH

RESET

VLVDHVxL

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