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LQFP64 Datasheet(PDF) 41 Page - STMicroelectronics |
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LQFP64 Datasheet(HTML) 41 Page - STMicroelectronics |
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41 / 116 page ![]() DocID14619 Rev 13 41/116 SPC560B40x/50x, SPC560C40x/50x Package pinouts and signal descriptions 115 3.11.2 NVUSRO[OSCILLATOR_MARGIN] field description The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. Table 10 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. 3.11.3 NVUSRO[WATCHDOG_EN] field description The watchdog enable/disable configuration after reset is dependent on the WATCHDOG_EN bit value. Table 11 shows how NVUSRO[WATCHDOG_EN] controls the device configuration. 3.12 Absolute maximum ratings Table 10. OSCILLATOR_MARGIN field description Value(1) 1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash. Description 0 Low consumption configuration (4 MHz/8 MHz) 1 High margin configuration (4 MHz/16 MHz) Table 11. WATCHDOG_EN field description Value(1) 1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash. Description 0 Disable after reset 1 Enable after reset Table 12. Absolute maximum ratings Symbol Parameter Conditions Value Unit Min Max VSS SR Digital ground on VSS_HV pins — 0 0 V VDD SR Voltage on VDD_HV pins with respect to ground (VSS) — 0.3 6.0 V VSS_LV SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) —VSS0.1 VSS+0.1 V VDD_BV SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) — 0.3 6.0 V Relative to VDD 0.3 VDD+0.3 VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) —VSS0.1 VSS+0.1 V VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) — 0.3 6.0 V Relative to VDD VDD 0.3 VDD+0.3 |
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