ADAU1761BCPZ-R7 datasheet(37/92 Pages) AD

37 / 92 page

Data Sheet

ADAU1761

CONTROL PORTS

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Rev. F | 37 of 92

The R/W bit determines the direction of the data. A Logic 0 on the

LSB of the first byte means that the main will write information to

the peripheral, whereas a Logic 1 means that the main will read

information from the peripheral after writing the subaddress and

repeating the start address. A data transfer takes place until a

stop condition is encountered. A stop condition occurs when SDA

transitions from low to high while SCL is held high. Figure 49 shows

the timing of an I2C write, and Figure 50 shows an I2C read.

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

with normal read and write operations, the ADAU1761 immediately

jumps to the idle condition. During a given SCL high period, the

user should only issue one start condition, one stop condition, or

a single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the ADAU1761 does not

issue an acknowledge and returns to the idle condition.

If the user exceeds the highest subaddress while in autoincrement

mode, one of two actions is taken. In read mode, the ADAU1761

outputs the highest subaddress register contents until the main

device issues a no acknowledge, indicating the end of a read. A

no acknowledge condition is where the SDA line is not pulled low

on the ninth clock pulse on SCL. If the highest subaddress location

is reached while in write mode, the data for the invalid byte is not

loaded into any subaddress register, a no acknowledge is issued by

the ADAU1761, and the part returns to the idle condition.

Figure 49. I2C Write to ADAU1761 Clocking

Figure 50. I2C Read from ADAU1761 Clocking

ADAU1761BCPZ-R7 Datasheet(PDF) 37 Page - Analog Devices