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ADAU1761BCPZ-R7 Datasheet(PDF) 50 Page - Analog Devices |
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ADAU1761BCPZ-R7 Datasheet(HTML) 50 Page - Analog Devices |
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50 / 92 page  Data Sheet ADAU1761 CONTROL REGISTERS analog.com Rev. F | 50 of 92 Table 33. Register Map (Continued) Reg Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R41 0x4030 Control Port Pad 1 Reserved SDASTR 00000000 R42 0x4031 Jack detect pin Reserved JDSTR Reserved JDP[1:0] Reserved 00001000 R67 0x4036 Dejitter control DEJIT[7:0] 00000011 R43 0x40C0 Cyclic redundancy check CRC[31:24] 00000000 R44 0x40C1 CRC[23:16] 00000000 R45 0x40C2 CRC[15:8] 00000000 R46 0x40C3 CRC[7:0] 00000000 R47 0x40C4 CRC enable Reserved CRCEN 00000000 R48 0x40C6 GPIO0 pin control Reserved GPIO0[3:0] 00000000 R49 0x40C7 GPIO1 pin control Reserved GPIO1[3:0] 00000000 R50 0x40C8 GPIO2 pin control Reserved GPIO2[3:0] 00000000 R51 0x40C9 GPIO3 pin control Reserved GPIO3[3:0] 00000000 R52 0x40D0 Watchdog enable Reserved DOGEN 00000000 R53 0x40D1 Watchdog value DOG[23:16] 00000000 R54 0x40D2 DOG[15:8] 00000000 R55 0x40D3 DOG[7:0] 00000000 R56 0x40D4 Watchdog error Reserved DOGER 00000000 R57 0x40EB DSP sampling rate setting Reserved DSPSR[3:0] 00000001 R58 0x40F2 Serial input route control Reserved SINRT[3:0] 00000000 R59 0x40F3 Serial output route control Reserved SOUTRT[3:0] 00000000 R60 0x40F4 Serial data/GPIO pin configuration Reserved LRGP3 BGP2 SDOGP1 SDIGP0 00000000 R61 0x40F5 DSP enable Reserved DSPEN 00000000 R62 0x40F6 DSP run Reserved DSPRUN 00000000 R63 0x40F7 DSP slew modes Reserved MOSLW ROSLW LOSLW RHPSLW LHPSLW 00000000 R64 0x40F8 Serial port sampling rate Reserved SPSR[2:0] 00000000 R65 0x40F9 Clock Enable 0 Reserved SLEWPD ALCPD DECPD SOUTPD INTPD SINPD SPPD 00000000 R66 0x40FA Clock Enable 1 Reserved CLK1 CLK0 00000000 CONTROL REGISTER DETAILS All registers except for the PLL control register are 1-byte write and read registers. R0: Clock Control, 16,384 (0x4000) Table 34. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved CLKSRC INFREQ[1:0] COREN Table 35. Clock Control Register Bits Bit Name Description 3 CLKSRC Clock source select. 0 = direct from MCLK pin (default). 1 = PLL clock. [2:1] INFREQ[1:0] Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is automatically set to 1024 × fS. |
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