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ADAU1761BCPZ-R7 Datasheet(PDF) 58 Page - Analog Devices

Part # ADAU1761BCPZ-R7
Description  SigmaDSP Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  92 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAU1761BCPZ-R7 Datasheet(HTML) 58 Page - Analog Devices

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Data Sheet
ADAU1761
CONTROL REGISTERS
analog.com
Rev. F | 58 of 92
Table 57. ALC Control 0 Register (Continued)
Bits
Bit Name
Description
101
18 dB
110
24 dB
111
30 dB
[2:0]
ALCSEL[2:0]
ALC select. These bits set the channels that are controlled by the ALC. When set to right only, the ALC responds only to the right channel
input and controls the gain of the right PGA amplifier only. When set to left only, the ALC responds only to the left channel input and controls
the gain of the left PGA amplifier only. When set to stereo, the ALC responds to the greater of the left or right channel and controls the gain
of both the left and right PGA amplifiers. DSP control allows the PGA gain to be set within the DSP or from external GPIO inputs. These bits
must be off if manual control of the volume is desired.
Setting
Channels
000
Off (default)
001
Right only
010
Left only
011
Stereo
100
DSP control
101
Reserved
110
Reserved
111
Reserved
R12: ALC Control 1, 16,402 (0x4012)
Table 58.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALCHOLD[3:0]
ALCTARG[3:0]
Table 59. ALC Control 1 Register
Bits
Bit Name
Description
[7:4]
ALCHOLD[3:0]
ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before increasing the gain to
achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent distortion of low frequency signals. The hold time
doubles with every 1-bit increase.
Setting
Hold Time
0000
2.67 ms (default)
0001
5.34 ms
0010
10.68 ms
0011
21.36 ms
0100
42.72 ms
0101
85.44 ms
0110
170.88 ms
0111
341.76 ms
1000
683.52 ms
1001
1.367 sec
1010
2.7341 sec
1011
5.4682 sec
1100
10.936 sec
1101
21.873 sec
1110
43.745 sec
1111
87.491 sec
[3:0]
ALCTARG[3:0]
ALC target. The ALC target sets the desired ADC input level. The PGA gain is adjusted by the ALC to reach this target level. The
recommended target level is between −16 dB and −10 dB to accommodate transients without clipping the ADC.
Setting
ALC Target



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