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TMP93CS41 Datasheet(PDF) 215 Page - Toshiba Semiconductor |
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TMP93CS41 Datasheet(HTML) 215 Page - Toshiba Semiconductor |
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215 / 248 page  TMP93CS40/TMP93CS41 2004-02-10 93CS40-213 (1) Read cycle Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. tRAH CLK X1 A0 to A23 CS0 to CS2 W R/ WAIT Port input (Note) RAS RD ALE tAK tAWH tCW tAWL tAPH2 tRP tRSH tRAS tASRL tRSC tCAC tCA tACH tACL tLC tRR tRAE tCL tOSC tCLK tKA tHR tRCD tADH tLA tAL tLL tCAS D0 to D15 AD0 to AD15 0 CAS to 2 CAS tAPH A0 to A15 tADL tRD tASRH tRAC |
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