L9305 datasheet(47/107 Pages) STMICROELECTRONICS

47 / 107 page

SPI

The SPI interface is used to configure the device, control the outputs and read diagnostic and status registers.

9.1

SPI protocol

The SPI protocol is defined by 32-bit frames with 5 bits of CRC (Cyclic Redundancy Check) for transmit and

receive. MOSI frame consists of an 8-bit address, 16-bit data, 5-bit CRC field and a one-bit frame counter. MISO

frame consists of SPI error and IC status information, address feedback, 16-bit data and 5-bit CRC field. SPI

communication uses various safety mechanisms to ensure high safety level coverage as defined in ISO26262

table D.8:

•

5-bit CRC check (Hamming distance of 3 over 26 bits data)

•

Frame Counter and Address Feedback

•

Timeout Monitoring

•

Short and Long Frame Length

All R/W registers are mirrored (i.e., simultaneously written with the same value) and the content of each main

register is verified with its related mirror register. Should a mismatch be detected, a fault flag is set. Details of this

safety feature are summarized in Section 8.6. The SPI frame format is shown in Figure 21.

Figure 21. SPI Frame Format

BIT

MOSI

MISO

Page

Idx

cnt

Data[n]

Data[n-1]

IndxFdbk

PageFdbk

IERR

CRC

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

GADG2709181448PS

The protocol implements Out of Frame response meaning the MISO output frame is related to the previous

transmitted MOSI frame as shown in Figure 22. The First SPI transfer after power on reset will have a fixed MISO

response consisting in the device ID.

Figure 22. Out of frame response

Frame #n

Add_#n

Data[Add_#n]

IC Registers

Data_#n = 0x0000

crc

Data_#n-1

Add_#n-1

Frame #n+1

Add_#n+1

Data_#n+1 = 0xYYYY

crc

Data_#n

Add_#n

GADG2709181450PS

Upon power on reset, the first SPI Frame will set all SPI fault bits and address bits to “0” and the data field will

contain the device ID as shown in Figure 23.

L9305

SPI

DS12774 - Rev 10

page 47/107

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