L9305 datasheet(25/107 Pages) STMICROELECTRONICS

25 / 107 page

To enable parallel mode the following conditions must be verified, otherwise the channels will be kept independent

depending on their own settings:

•

Bit 14 and/or Bit15 in SERVENA register must be set to 1 (Bit14 enables parallel mode for ch0-ch1 pair,

Bit15 for ch2-ch3 pair)

•

SOLENDRV configuration must be equal for selected parallel channel pair

Even if diagnostic is kept independent, faults causing tri-state condition will affect both channels in parallel mode.

Parallel mode is mandatory to use only with maximum slew rate setting and in configuration HILOAD=0. Besides,

driver active time (T_ON) must be higher than a minimum value, which directly depends on load current, battery

voltage applied to the solenoid and load parameters.

Further guidelines on the usage of this feature are provided in a specific dedicated Application Note.

6.1.9

Dither programming

Dither programming (Channel_x.DITHPGM1 and Channel_x.DITHPGM2) superimposes a triangular amplitude

modulation on the current set point as shown in the Figure 13.

Figure 13. Dither waveforms definitions

Tdither[s] = 4 · Nstep · Tstep[s]

Tdither[s] = 4 · Tstep[s]

Tdither[s] = 2 · Tstep[s]

Example of Nstep = 3

Example of Nstep = 1

Example of Nstep = 0

Tstep[s]

Istep

(3)

(1)

(2)

(1)

3 steps

Isetpoint

Istep

GADG2709181243PS

To implement dither function, the following parameters need to be set according to the user operating

requirements.

•

Tstep: Dither step time duration is programmable as an integer number of PWM periods as defined by the

formula

DitℎerStepDuration= Tstep+1*Tpwmwhere:

–

Tstep is programmable in Channel_x.DITHPGM2, D[5:0].

–

TPWM is the PWM period programmable in Channel_x.CTRLCFG register, D[10]

•

Nstep: number of steps in a quarter of a dither period, where:

–

Nstep is the value programmed in Channel_DITHPGM2 register, D[12:8]

–

If Nstep = 0, a square wave dither of 2 steps peak to peak will be generated

•

Istep: Current step amplitude is programmable in Channel_xDITHPGM1 register, D[7:0] with the same

current resolution as the current set point.

–

HILOAD = 0 → Normal current mode - Single bit resolution = 0.25 [mA] - Max Step Current

63.75[mA];

DitℎerStepCurrent=Istep7:0*0.25mA

–

HILOAD = 1 → High current mode - Single bit resolution = 0.33 [mA] - Max Step Current 84.15[mA].

DitℎerStepCurrent=Istep7:0*0.33mA

•

Tdither: Dither period calculated as:

Tditℎer=4*Nstep*Tstep

•

Idither: Peak-to-peak current modulation amplitude calculated as:

Iditℎer=2*Nstep*Istep

Dither can be enabled/disabled via SPI in register Channel_x.DITHPGM1, D[15]. Dither waveform maximum

amplitude is limited by the selected current resolution configuration (HILOAD, register CONFIGURATION1, D[15])

as shown below:

HILOAD = 0 → Normal current mode - Max Dither Current Amplitude = ± 250 [mA];

HILOAD = 1 → High current mode - Max Dither Current Amplitude = ± 330 [mA];

L9305

Current control drivers

DS12774 - Rev 10

page 25/107

L9305 Datasheet(PDF) 25 Page - STMicroelectronics

L9305 Datasheet(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL