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L9305 Datasheet(PDF) 55 Page - STMicroelectronics |
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L9305 Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 107 page  TIMEOUTSPICFG Timeout SPI configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RW RW RW RW Address: Global Base Address + 0x02 Type: RW Reset: 0x0028 Description: SPI TIMEOUT Configuration Register [15:7] Unused [6:5] Number of SPI timeout events to force an internal reset Timeout NR Reset [1:0]; Calculated as 2^(N+1) (e.g., default N= "01", Timeout Events = 4) [4:2] Maximum time between valid SPI frames before SPI time-out fault flag is set.Timeout Configuration [2:0]: Calculated as follows: 504 x 2N [µs] (e.g., default N=B“010” means 2016 [µs]) [1] Enable Reset Latch - En_Res_Latch[1]: 0: Reset Latch Disabled 1: Reset Latch Enabled [0] Disable Reset Latch - Dis_Res_Latch[0] 0: Reset Latch Enabled 1: Reset Latch Disabled L9305 SPI DS12774 - Rev 10 page 55/107 |
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