SPC560B50x datasheet(38/116 Pages) STMICROELECTRONICS

38 / 116 page

Package pinouts and signal descriptions

SPC560B40x/50x, SPC560C40x/50x

38/116

DocID14619 Rev 13

PH[7]

PCR[119]

AF0

AF1

AF2

AF3

GPIO[119]

E1UC[9]

CS3_2

MA[1]

SIUL

eMIOS_1

DSPI_2

ADC

I/O

Tristate

—

137

PH[8]

PCR[120]

AF0

AF1

AF2

AF3

GPIO[120]

E1UC[10]

CS2_2

MA[0]

SIUL

eMIOS_1

DSPI_2

ADC

I/O

Tristate

—

138

PH[9](9) PCR[121]

AF0

AF1

AF2

AF3

GPIO[121]

—

TCK

—

SIUL

—

JTAGC

—

I/O

—

Input, weak

pull-up

127

PH[10](

PCR[122]

AF0

AF1

AF2

AF3

GPIO[122]

—

TMS

—

SIUL

—

JTAGC

—

I/O

—

Input, weak

pull-up

120

Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00

 AF0;

PCR.PA = 01

 AF1; PCR.PA = 10  AF2; PCR.PA = 11  AF3. This is intended to select the output functions; to use

one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields.

For this reason, the value corresponding to an input only function is reported as “—”.

Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the

values of the PSMIO.PADSELx bitfields inside the SIUL module.

LBGA208 available only as development package for Nexus2+

All WKPU pins also support external interrupt capability. See wakeup unit chapter for further details.

NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.

“Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the

reference manual for details.

Value of PCR.IBE bit must be 0

Be aware that this pad is used on the SPC560B64L3 and SPC560B64L5 to provide VDD_HV_ADC and VSS_HV_ADC1.

Therefore, you should be careful in ensuring compatibility between SPC560B40x/50x and SPC560C40x/50x and

SPC560B64.

Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.



PC[0:1] are available as JTAG pins (TDI and TDO respectively).



PH[9:10] are available as JTAG pins (TCK and TMS respectively).



If the user configures these JTAG pins in GPIO mode the device is no longer compliant with IEEE 1149.1-2001.

10. The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY

mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an

input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra

consumption TDO must be connected. An external pull-up resistor in the range of 47–100 k

 should be added between the

TDO pin and VDD_HV. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down

resistor with the same value should be used between TDO pin and GND instead.

Table 6. Functional port pin descriptions (continued)

Pin number

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